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Curtiss-Wright Low Power Processing Card Runs Linux/DSP BIOS on Multicore TI OMAP-L138

The Defense Solutions division of the Curtiss-Wright Corporation has announced that it will launch a new softwarel138 card development multicore processor module, the MAT/101. The module is designed for use with its Acra KAM-500 digital data acquisition unit (DAU) systems.

The company claims that the MAT/101 will improve and simplify the building of custom applications for mission critical airborne applications such as flight testing, usage monitoring and other recording needs.

TI Opam l138The MAT/101 is based on Texas Instruments’ OMAP-L138 embedded platform, which houses both an ARM 9 core and a TI digital signal processor (DSP). Linux is typically supported on the ARM while DSP BIOS or another DSP realtime operating system such as Enea OSEck runs on the DSP communication between cores is handled by an inter-process communications technology like DSPLink or LINX. The MAT/101 will have a number of software development kits to select from. For more on programming the OMAP-L138 see this video: Enea Optima Debugging Heterogeneous Multicore System based on TI OMAP-L138

Connectivity for the MAT/101 includes Ethernet, GPIO and RS-232 delivering debugging, read/write parameters and triggering of external circuits. Support for DAS Studio software simplifies the selection of values to be accessed in an application, and eliminates the complexities of parameter placement and timings.

Lynn Bamford, Senior Vice President & General Manager, Defense Solutions division said: “Adding the new MAT/101 processor board to a KAM-500 data acquisition system allows system designers to rapidly develop custom software for critical applications such as data reduction and exceedance flagging for usage monitoring. The MAT/101 module opens up a host of data acquisition application possibilities such as NMEA message parsing, fuel level tracking, and processing data prior to telemetering to ground. It also eliminates the need for a separate computer for reading and issuing SNMP commands in an Ethernet network.”

Release of the MAT/101 is planned for the second quarter of 2014.

Key feature of the TI OMAP-L138 include:

Dual-Core SoC

  • 375- and 456-MHz ARM926EJ-S RISC MPU
  • 375- and 456-MHz C674x Fixed- and Floating-Point VLIW DSP

ARM926EJ-S Core

  • 32- and 16-Bit (Thumb) Instructions
  • DSP Instruction Extensions
  • Single-Cycle MAC
  • ARM Jazelle Technology
  • Embedded ICE-RT for Real-Time Debug

ARM9 Memory Architecture

  • 16KB of Instruction Cache
  • 16KB of Data Cache
  • 8KB of RAM (Vector Table)
  • 64KB of ROM

C674x Instruction Set Features

  • Superset of the C67x+ and C64x+ ISAs
  • Up to 3648 MIPS and 2746 MFLOPS
  • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
  • 8-Bit Overflow Protection
  • Bit-Field Extract, Set, Clear
  • Normalization, Saturation, Bit-Counting
  • Compact 16-Bit Instructions

C674x Two-Level Cache Memory Architecture

  • 32KB of L1P Program RAM/Cache
  • 32KB of L1D Data RAM/Cache
  • 256KB of L2 Unified Mapped RAM/Cache
  • Flexible RAM/Cache Partition (L1 and L2)

Enhanced Direct Memory Access Controller 3 (EDMA3):

  • 2 Channel Controllers
  • 3 Transfer Controllers
  • 64 Independent DMA Channels
  • 16 Quick DMA Channels
  • Programmable Transfer Burst Size

TMS320C674x Floating-Point VLIW DSP Core

  • Load-Store Architecture with Nonaligned Support
  • 64 General-Purpose Registers (32-Bit)
  • Six ALU (32- and 40-Bit) Functional Units
  • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  • Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks
  • Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
  • Two Multiply Functional Units:
  • Mixed-Precision IEEE Floating-Point Multiply Supported up to:
  • 2 SP x SP → SP Per Clock
  • 2 SP x SP → DP Every Two Clocks
  • 2 SP x DP → DP Every Three Clocks
  • 2 DP x DP → DP Every Four Clocks
  • Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
  • Instruction Packing Reduces Code Size
  • All Instructions Conditional
  • Hardware Support for Modulo Loop Operation
  • Protected Mode Operation
  • Exceptions Support for Error Detection and Program Redirection
  • Software Support

TI DSPBIOS

  • Chip Support Library and DSP Library
  • 128KB of RAM Shared Memory
  • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)

Two External Memory Interfaces:

  • EMIFA
  • NOR (8- or 16-Bit-Wide Data)
  • NAND (8- or 16-Bit-Wide Data)

16-Bit SDRAM with 128-MB Address Space

  • DDR2/Mobile DDR Memory Controller with one of the following:
  • 16-Bit DDR2 SDRAM with 256-MB Address Space
  • 16-Bit mDDR SDRAM with 256-MB Address Space

Three Configurable 16550-Type UART Modules:

  • With Modem Control Signals
  • 16-Byte FIFO
  • 16x or 13x Oversampling Option

LCD Controller

  • Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects
  • Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O (SDIO) Interfaces
  • Two Master and Slave Inter-Integrated Circuits

 

 

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